1. Field of the Invention
The present invention relates to arc detection and, in particular, to a method and apparatus for detecting arcs during sputter deposition.
2. Problem to be Solved
Physical Vapor Deposition (PVD), also known as sputtering, is a process for forming thin metal layers on wafers used for integrated circuits (ICs). The technique requires the use of a typical PVD sputter chamber 10 illustrated in FIG. 1 which includes vacuum chamber 11. The technique is generally performed according to the following description. A target 12 formed of a material such as a metal or insulator is placed in a vacuum chamber 11 and connected electrically as a cathode. An anode 13 provides reference to ground. An electric field placed between the target 12 and the anode 13 by a power supply 15 causes a low pressure gas, such as argon, to ionize. Ionized gas atoms are accelerated across the electric potential and impact the target 12 at high speed, causing target metal atoms to be physically removed or sputtered. The metal atoms ejected from the target material travel virtually unimpeded through the low pressure gas and plasma and strike substrate 14 forming a coating having an approximately uniform thickness.
Arcing occurs when a path from ground to the target is established through electrons or ions in the plasma. Arcing during PVD can be caused by factors such as contamination or inclusion within the structure of the target or from such tool maintenance factors as contamination from other sources such as vacuum grease, vacuum leaks, or improper alignment of the target. Contaminants in the target, referred to as inclusions, can include SiO.sub.2 or Al.sub.2 O.sub.3. Arcing during PVD carl cause damage to semiconductor chips on a wafer and reduce the yield of good chips on the wafer. While normal metal deposition is typically less than 1 micron thick, the arcing causes a locally thicker deposition of metal on the wafer. Subsequent processes are used to pattern and etch metal lines onto the wafer. Since the local defect is thicker than the surrounding metal, the defect is not etched through in the subsequent processing, and this can result in a short circuit on the chip. The local defect can also distort a pattern imaged onto the wafer in a subsequent photolithography step. A semiconductor chip has multiple levels of metal lines separated by an insulator, each of the metal levels formed by a process such as: sputter depositing the metal, patterning the metal, and etching the metal. Since a metal short at any level will cause the chip to fail, it is important to avoid damage from arcing during sputter deposition.
Prior art deposition chambers run until the target inclusion which caused the arc is sputtered through or the arc causing problem is fixed. Corrective action is dependent upon the availability of parametric data, for example, the number of metal shorts per layer, or inspection based upon a sample plan which reveals the defects. This information can take weeks to obtain. As a result, both random yield loss and yield loss for an extended time remain undetected.
The effects of arcing have been detected by scanning the surface of wafers after metal deposition with a laser, a costly process. Reliable techniques for finding inclusions in targets that might cause arcing have not been available, and claims by target manufacturers that their targets have low inclusion levels could not previously be substantiated by wafer surface scanning techniques. Furthermore, no process was available to provide real-time monitoring of the arcing in the deposition chamber.